(1) Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, it relates to a metal-insulator semiconductor (MIS) dynamic memory device in which a plurality of sense amplifiers are selected by a single decoder circuit and the number of conducting patterns connected to the decoder circuit is decreased.
(2) Description of the Prior Art
To increase the degree of integration of a semiconductor memory device, it is necessary to effectively use the chip area of the integrated circuit of the memory device. In an attempt to do this, a recent MIS dynamic memory device adopts a system in which two sense amplifiers are selected by one decoder circuit instead of using a system in which one decoder circuit selects one sense amplifier.
However, in the MIS dynamic memory device using the system in which two sense amplifiers are selected by one decoder circuit, the number of conducting patterns connected to each decoder circuit is relatively large, and, therefore, the conducting patterns occupy large areas of a semiconductor chip so that it is difficult to increase the degree of integration of the memory device. Moreover, since each of the long conducting patterns has a relatively large electrostatic capacitance, the drive capacity of a drive circuit such as a buffer amplifier circuit must be large. Accordingly, the size of the drive circuit becomes large and the speed of selecting the sense amplifiers becomes slow.